1. Field of the Invention
This invention relates to a switching power source apparatus for DC—DC conversion which performs a constant voltage control with a current limit function.
2. Description of the Related Art
Conventionally, a current limit by pulse-by-pulse method has been adopted for many switching power sources which perform the constant voltage control with a function of the current limit.
FIG. 5 is a view showing the configuration of a conventional switching power source for constant voltage control which performs the current limit by the pulse-by-pulse method.
As seen from FIG. 5, between a power source voltage VCC and ground, a current detecting resistor 51, a high-side switch 52 which is an NMOS transistor (hereinafter, referred to “NMOS”), and a low-side switch 53 which is an NMOS are connected in series. From a connecting point of the high side switch 52 and the low side switch 53, an output voltage Vout is produced through a smoothing coil 54 and a smoothing capacitor 55. Reference numeral “60” denotes an IC for a regulator.
The output voltage Vout is fed back to an error amplifier 61, and compared with a reference voltage Vref1. A feedback voltage FB, which is an error output, is produced from the error amplifier 61. The feedback voltage FB and a triangular wave signal supplied from a triangular wave oscillator 62 are compared by a PMW comparator 63 to create a PWM signal. The PWM signal, after passed an AND circuit 64, becomes a gate driving signal P1 through a driver 65. The gate driving signal P1 is supplied to the gate of the high side switch 52. The PWM signal, after passed the AND circuit 64, also becomes a gate driving signal P2 through a delay circuit 66 and an inverting driver 67. The gate driving signal P2 is supplied to the gate of the low side switch 53.
By the gate driving signal P1 and gate driving signal P2, the high-side switch 52 and the low-side switch 53 are alternately turned on and off. The on/off time width is automatically adjusted by PWM control to produce a preset output Vout.
On the other hand, for the purpose of a current limit operation, the detecting resistor voltage ΔV due to the current I flowing through the current detecting resistor 51 is always monitored. The detecting resistor voltage ΔV is compared with a reference voltage Vref2 in a comparator 68. If the current I is smaller than a prescribed limited current, the detecting resistor voltage ΔV is smaller than the reference voltage Vref2 (ΔV<Vref2). In this case, the output from the comparator 68 is at a high (H) level so that the AND circuit 64 permits the PWM signal to pass.
If the current I exceeds the prescribed limited current, the detecting resistor voltage ΔV is larger than the reference voltage Vref2 (ΔV>Vref2). In this case, the output from the comparator 68 is at a low (L) level so that the AND circuit 64 does not permit the PWM signal to pass. As a result, the high-side switch 52 is turned off and the low-side switch 53 is turned on, thereby limiting the current I.
In some voltage PWM inverters, the output current is monitored to reduce a set voltage value when the output current exceeds a prescribed value.
JP-B-H7-55055 is known as a related art.
In a conventional switching power source apparatus for constant voltage control which performs the current limit by the pulse-by-pulse method, since the current is detected with using the detecting resistor voltage ΔV generated in the current detecting resistor 51 due to the current, the gate driving signal P1 must be stopped while the high-side switch 52 is ON.
The delay time from when the detecting resistor voltage ΔV exceeds the reference voltage Vref2 to when the gate driving signal P1 actually stops exerts an influence on the accuracy of current limit to deteriorate the accuracy as the delay time increases. In addition, due to the pulse-by-pulse method, the influence by the delay occurs repeatedly during each pulse cycle. Therefore, in order to carry out the current limit with high accuracy, a high speed comparator 68 (having e.g. a response of about several ns (nano seconds)) is required and further the delay time of the driver 65 must be decreased. However, it is difficult to implement the high speed operation of these comparator 68 and driver 65.
Further, since passage or block of the PWM signal is controlled by using the output from the comparator 68, the output voltage is likely to be unstable by the switching operation at the time of current limit.